资源列表
ACCx42_AvalonST_Input
- This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices
APBL
- APBL通信协议的FPGA设计，适用于高速通讯(APBL communication protocol FPGA verilog design)
AHB_LITE
- AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
AD胡
- 用FPGA开发板实现FIR滤波器，C2000 DSP教学实验箱(Implementation of FIR filter with FPGA development board)
csa_codes
- carry_select_adder for 16-bit in verilog
Desktop
- 用Verilog编程语言来实现一个具有奇校验功能的串行发送电路，可以采用移位寄存器和有限状态机的方式来实现。(Serial transmission circuit with odd check function)
xyj
- 实现洗衣机六个状态的转换，计时、报警功能。(The realization of the conversion, timing and alarm function of the six states of the washing machine.)
gtx_aurora_zc706_clock_module
- 对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
CRC
- CRC32:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8 CRC16:polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) * data width: 8
DIGITALCLOCK
- 多功能数字种 可实现校时 闹钟 整点报时等功能(Multi-function digital species can realize the function of time alarm clock and other functions)
PLL
- verilog编写的锁相环程序。可以对照参考(Verilog prepared by the phase-locked loop program. Can control reference)
按键消抖
- 按键消抖比较实用的代码 对于入门的同学很实用(A more practical code with a button.)