资源列表
Pall_FIR
- FIR低通滤波器得设计，采用并行算法设计
MAC-DATA
- MAC UNIT DOCUMENTATION
spartan6_GTP
- 基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)
ADS8509
- FPGA驱动高输入电压范围的ADS8509芯片，采样范围广，适合前端大信号处理-FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing
zldj.rar
- 一种直流电机伺服系统的设计，其中包括了各种控制模块的VHDL语言,A kind of DC motor servo system design, including the various control modules of VHDL language
数字钟(8)
- 数字钟（总）整点报时，8位数码管显示。VHDL语言设计。。。。(Digital clock (total) the whole point timekeeping, 8 digital display. VHDL language design....)
CardBusIP_v1.0
- VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE
modelsim-ALTERA-manual
- 经常的modelsim使用手册，和Altera公司的FPGA软件配套使用-Regular modelsim manual, and Altera' s FPGA software supporting the use of
mc8051_cyclone_nios
- 增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
ryg
- 双模交通灯系统，实现交通灯不同通断时间控制方案，及手动控制，基于VHDL语言，DB2平台，时间通过数码管显示-Dual-mode traffic light system, different traffic lights-off time control scheme, and manual control, based on the VHDL language, DB2 platform time through the digital display
mc8051_cyclone_nios
- mc8051 v1.4 oregano VHDL core for the Altera Cyclone Nios evaluation board.
System_Verilog_for_Verification
- System Verilog for Verification