资源列表
lect-2a[3]
- slides of vhdl chap no 2 -slides of vhdl chap no 2 ...
dds_new
- 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
DE2_USB_API
- 基于altera DE2开发板的USB应用程序，可以实现对FPGA的各项控制，包括输入数据到SRAM中，更换VGA显示器显示的图片等-Based on altera DE2 development board USB application process can be achieved with the control of the FPGA, including the input data to the SRAM, the replacement of VGA display pictur
fpga_frame
- 测试代码，利用fpga发送一帧一帧的raw视频，用于DSP接受和测试-Test code, using fpga send a raw video frame by frame, for receiving and testing of DSP
Verilog-Coding-Style-Proposal_final
- Verilog 开发规范 让你的程序易读易用-verilog coding style
xc2s100
- xc2s100E FPGA的原理图 给想涉足FPGA的新人参考
divider
- 用VHDL实现了一个计时器，在SPANTAN3E上验证通过-VHDL, implements a timer, in the SPANTAN3E verified by the
Servicemanual_Belinea_101910_artno_111908
- Service manual for LCD monitor 19" Belinea part No. 101910 to 111908
e7v4
- 数字钟：显示，设置时间，设置闹铃（报时），秒表。 平台：quartusII 5.1。 说明：此版本中已将系统时钟调快，自己稍微改动一下即可，小小的考验，做出来会更有成就感！-digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
XS3S1000
- XILINX公司XC3S1000FGG456下的VHDL工程,主要完成AD采用以及和CPU的数据交换-XC3S1000FGG456 s program example
versatile_counter_latest.tar
- 有用的verilog EDA代码，好像是内核，不知道有没有用-verilog EDA
ROCE_PCI_LED
- pci9054 上下位机通信下位机代码 -verilog project for the communication between PC and PCI board.