资源列表
fast-fft
- 关于高速FFT的FPGA实现的一份资料 OFDM 的基本原理 定点 FFT 分析-On high speed FFT FPGA to achieve a basic principle of OFDM fixed-point FFT analysis
ceping1
- 基于ＦＰＧＡ的一个频率计的设计，希望对有需要的朋友们有所帮助。很是简单的一个东西，希望大家一起改进-FPGA-based design a frequency counter, and I hope there is a need to help friends. It is simply a thing, I hope everyone Improved! ! !
cpu
- cpu的vhdl设计实现加法减法乘法运算-cpu VHDL Design and Implementation of multiplication addition subtraction
signal-generator
- 进阶实验_16_DA[DA9708] ：输出正弦、方波、三角、锯齿(频率、幅度连续可调)-Advanced experimental _16_DA [DA9708] : output sine, square, triangle, sawtooth (frequency, amplitude adjustable)
fifo_env
- for synchronization when we are dealing with 2 different clock domain
Verilog_digital_clock
- Digital clock using Quartus9.1 platform, using Verilog language, to share to everyone
FULL-FPGA-SCH
- 包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.-Including the Cyclone II EP2C20 schematic . Cycl
delay_add
- 利用Vivado高层次综合实现的用HDL语言描述的时序的delay函数-realize a delay function, which is described by the Verilog, by Vivado
project_zyg
- 利用HC——SR04的超声波模块与EGO1板子外加一个EMAX电机形成一个测距报警器 上传文件为vivado程序(Using the HC - SR04 ultrasonic module and the EGO1 board plus a EMAX motor to form a range finder to upload the file as the vivado program)
reset
- project2 in vhdl xilinx sparten 3-project2 in vhdl xilinx sparten 3
sp605_MIG_rdf0029_13.4_c
- XILINX评估板sp605的FPGA MIG使用参考文档(The FPGA MIG of the XILINX evaluation board sp605 uses a reference document)
t12
- quartus 9.0的工程，verilog编写，步进电机控制，可以调速和控制位置.可综合。-Quartus project files are included in RAR file. It s written in verilog HDL ,and the purpose is to control both the speed and position of Stepper motor。And project passed synthesis.