资源列表
usb_sim_model
- EZ-USB的仿真模型，Verilog实现，能够实现端点传输，自用。-EZ-USB simulation model, Verilog implementation, to achieve the endpoint transmission, personal use.
vhdl
- VHDL实验报告 基于ROM的正弦波发生器的设计-VHDL experiment reports the ROM-based sine wave generator design
fourroadccd
- 一种CCD采集模式，思路采集，每路12位，思路同时实现48位高速传输。-A CCD acquisition mode, collection, each road 12, thinking the 48 high-speed transmission at the same time.
shj
- 基于fpga的自动售货机，verilog编写，源码内有详细说明-Fpga-based vending machine, verilog prepared with a detailed descr iption of source
abmodp
- 加运算法中的求佘运算。abmodp.generate the control signals for calculating abmodp-Increase in the demand algorithm She operations. abmodp.generate the control signals for calculating abmodp
FPGA_statu-machine
- FPGA 编程中常用的状态机编写风格和代码。开发环境为ISE10.1.-FPGA programming state machines commonly used in writing style and code.Development environment for ISE10.1.
ccd
- 自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴-Of write a tcd1209d of timing-driven code, Verilog language, can learn from
Trafficsignalcontroller
- 交通灯控制器 在十字路口的两个方向上各设一组红绿黄等，显示顺序为：其中一个方向是绿灯，黄灯，红灯，另一个方向是红灯，绿灯，黄灯。-Traffic signal controller at the crossroads of two directions, each with a set of red, green and yellow, shows the following order: one direction is green, yellow, red, and the other
multi
- VHDL Multiplier RTL code-VHDL Multiplier RTL code
vsb
- modulation in matlab
irq
- Universal Initiolizator processings of interruptions (for NIOS2)
bb
- 2选1的数据选择器 实现2选1的电路功能，其真值表和电路符号如下图所示。即当s＝1时，输出m＝y；当s＝0时，输出m＝x。 -2 Select a data selector circuit to achieve 2 S 1 function, its truth table and circuit symbols shown below. That is, when s = 1, the output m = y when s = 0, the output m = x.