资源列表
dotdisplay
- 16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！-16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!
a-floating-point-adder
- 一个浮点加法器，verilog描述，数据格式：高14位为尾数，低四位位指数（带符号数运算）-A floating point adder Verilog descr iption
DS18B20
- DS18B20数码管显示温度，vhdl语言编写，可移植模块-DS18B20 digital display temperature, VHDL language, portable module
display_input
- 用VHDL控制LCD12864输出指定文字-Using VHDL output control LCD12864 specified text
original-1-by-16-bit-multiplier
- 原码一位乘16位乘法器 用VerilogHDL语言实现-Original code A by 16-bit multiplier VerilogHDL language used to achieve
REJ
- bulilt in self test and repairable
DS18B20
- ds18b20数码管显示温度 开发板型号:A-C8V4-ds18b20 development board temperature digital display Model: A-C8V4
LED
- LED流水灯程序，可以实现安50分频的频率流水，文件中值包含了必要的.v文件，具体工程需要自己创建-LED light water program, can realize frequency water, Ann 50 points frequency value of the file containing the necessary. V file, need to create your own specific project
802.1as
- 802.1as gptp标准包解析verilog模块。用于实现EAVB协议的重要部分。-802.1as gptp verilog module, part of EAVB procotol
multiplier.tar
- 用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过-Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
graycnt_14
- 14位格雷码计数器的verilog描述及仿真波形-14-bit Gray code counter verilog descr iption and simulation waveforms