资源列表
mini_fifo
- 另外一个用VHDL源码编写的FIFO模块程序,可以比较一下和FIFO有什么区别.-Another, prepared by using VHDL source FIFO module procedures, you can compare and What is the difference between FIFO.
JTAG
- altera usb_blaster 的jtag驱动代码-altera usb_blaster the jtag driver code
Altera_ip_core
- Altera公司的PWM_VerilogHDL源码-Altera Corporation PWM_VerilogHDL source
10bit_Booth_algorithm
- 10位加法器，booth算法对学习computer architecture有帮助-10-bit adder, booth algorithm is useful for learning computer architecture
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of
TLC
- 用VHDL语言写的交通灯控制器，希望对大家有所帮助。-VHDL language with the traffic light controller, you would like to help.
Common-multiplier-design
- 常用乘法器设计，用FPGA能实现，值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.
shuzinaozhong
- 一个数字闹钟的vhdl代码！ 分成几个模块 要通过自顶向下的设计方法来做！-A digital clock vhdl code! Divided into several modules through top-down design method to do!
lift_three
- 三层电梯控制系统 verilog语言编写，能够实现基本功能-system of lift_three controller
DS1820
- DS18B20温度传感器，用verilog语言实现-DS18B20 temperature sensor, with the verilog language
电梯控制电路
- 电梯控制电路，用verilog写-elevator control circuit used to write Verilog
rec_buf
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.