资源列表
huffman
- 用verilog硬件语言实现了动态huffman编码，能够压缩字符串文件，展示了硬件的压缩率-Using verilog hardware descr iption language to achieve a dynamic huffman coding to compress the string file, showing the hardware compression rate
ee2
- 多功能时钟，可预设时间，可预设闹钟，可调数码管亮度，选择调整时，数码管被选中位会闪动-Multi-clock, preset time, preset alarm clock, adjustable LED brightness, select the adjustment, LED will flash the selected bit
24mod
- 模24计数器 自己可调成多种计数器 功能强大-24 adjustable mold into a variety of counter counter their powerful
adcontrol
- 采用VHDL编写的FPGA的AD转换读取逻辑。AD器件为TI ADS7961 -FPGA using VHDL prepared to read the AD conversion logic. AD device is a TI ADS7961
urisc_2011
- 这是一个urisc的作业，用于搭建一个单指令的处理器，-This is a urisc job, build a single instruction for the processor,
fifo_code
- FIFO读空标志和写满标志的计算，memory分配-FIFO read empty flag and filled with flag calculation, memory allocation
uC_CISC_16_Design
- Verilog Based CISC Processor.....Availble for Purchase...rahulshandilya@outlook.com
serial-port
- 串口数据采集 包括打开串口和串口初始化函数，在自己开发板测试需更改串口名称-serial port
xunhuan
- 编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.
20FIRfilterwithCSD
- 20阶FIR滤波器，用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters
uart2iic
- uart2iic using - Verilog source for I2C module
alarm_clock
- alarmclock fpga clock