资源列表
reg_16
- 16位寄存器 16位寄存器 -16-bit register,16-bit register16-bit register
matlab
- matlab中的无线信道仿真与实现。欢迎分享，分享快乐。-The wireless channel simulation and realization in matlab.Welcome to share, share the happiness.
fir
- FIR滤波器的FPGA仿真与实现。欢迎分享，分享快乐。-The FPGA simulation and realization of the FIR filter.Welcome to share, share the happiness.
Verilog-tutorial
- verilog语言教程 HDL语言的速成指南-Quick Guide verilog HDL language language tutorial
CNT999
- 使用VHDL设计999加法计数器，并使用扫描译码电路将数字显示在数码管上。顶层设计使用的原理图-Design using VHDL adder 999 counters, and use the digital scan decode circuit in the digital tube display. Schematic top-level design using
ECC in VHDL implementation
- ECC Cryptography is a very Good Cryptography Compared to other public key cryptography, it is helpful for both computationally intensive and resource constrained devices for information security purpose. hope you will enjoy
ECC in VHDL
- ECC Cryptography in VHDL . Very Helpful for showing
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is
ethernet_test_top
- Ethernet Code for Spartan6 FPGA
pwm
- VERILOG 学习第一课，输出一定占空比方波-VERILOG learn the first lesson, a certain duty cycle square wave output
8B_10BENCODER
- 基于8B10B的编解码模块的设计，使用verilog HDL语言，具有实用价值。-8B10B encoder
CCSDS_H1_yxiao
- CCSDS标准的LDPC编码的MATLAB仿真源码-CCSDS standard LDPC coding MATLAB simulation source