资源列表
diexing
- VHDL编写的蝶形变换，可用于FFT变换-VHDL prepared by the butterfly transform, FFT can be used to transform
RAM
- Ram with 8 bits implemented in vhdl verilog code
counter
- simple counter for demonstration purposes
Carry_Select_Adder_Verilog
- 进位选择加法器，verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.
multiwayselector
- 基于verilog硬件描述语言的多路选择器-Verilog hardware descr iption language based on multi-way selector
qudong
- 实现驱动红外探测器前端图像采集功能，实现红外热成像镜头的前端采集。-Infrared detector drive to achieve front-end image acquisition, to achieve front-end collection of infrared thermal imaging lens.
fpgashiyi
- FPGA 开发实例，加法器，乘法器，计数器等-examples of FPGA
cfar_fsm
- Cell averaging CFAR is implemented in this package
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合
ALU
- This MIPS ALU verilog code-This is MIPS ALU verilog code
crc_gen.pl
- CRC verilog 生成脚本，可自己设定CRC 参数-CRC verilog generate scr ipts, you can set their own parameters CRC
boothradix4
- VHDL code for Radix 4 booth multiplier