资源列表
LIBRARY-IEEE
- 8位数码管的动态显示（包括对数码管的位选以及段选）-8 digital control dynamic display
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
gai
- 波特率可供选择的vhdl源程序,已调试无错误
spi
- 基于verilog 的SPI实现，方便移植
2410_buttons
- FPGA中的设计全过程，有助于对FPGA和VHDL的认识，好好研学吧！
XianShiRiQi(weizhun)
- 数码管显示日期，用verilog语言书写，8个数码管可循环左移-Digital tube display the date, written in verilog language, eight digital tube can be cyclic shift to the left
bingchuan
- 简单的vhdl的四位并串转换程序，可以实现数据的并串转换-Simple vhdl string of four and the conversion process, can convert the data and the string
PART5
- LAB 2 _ level 2 for verilog
Div_Fre
- 5分频器，功能是对需要信号进行五分频，生成周期为原来五倍的信号-5 divider, the fifth of the frequency on the need to signal the build cycle for the original five times the signal
audioloopback
- Verilog program for running a audio loopback system for AC97 codec.
exp13_7
- 竞赛抢答器:控制8255,C口作为输入,从A口输出与之对应的LED段码-race Responder : Control 8255, C mouth as input, output from the A-corresponding to the code of LED
eclock
- 定时器的编程，vhdl语言，可以实现24时制定时器