资源列表
running-water-led
- 流水灯程序，采用组合逻辑。内有仿真文件。是FPGA开发必须学的一个程序-Light water program, using a combination of logic. There simulation files. Is a program FPGA development must learn
CT74125
- 一个四总线缓冲器设计，亲测好使。适合初学者。FPGA开发-A four-bus buffer design, pro-test so. Suitable for beginners. FPGA Development
music
- 用蜂鸣器播放音乐的verilog例程，音乐为致爱丽丝-Play with verilog routines buzzer music, music Zhiailisi
I2C_control
- I2C两线式串行总线的控制端的verilog源代码，经过编译和modelsim仿真后是正确的！-Two-wire I2C serial bus control terminal verilog source code, after compiling and modelsim simulation is correct!
NiosIISPI
- NiosII上spi总线的设计，源代码简洁易懂，有助于学习者读懂和移植-NiosII on spi bus design, source code easier to understand, to help learners understand and transplantation
fifo_csm
- 一个先进先出的描述代码，用于实现先入先出的操作-first in first out
digitalvoltemterdesign
- FPGA的关于数字电压计的设计源代码，已验证可行-FPGA on the digital voltmeter design source code, has been proven feasible
FPGA_cymometer
- FPGA程序，verilog HDL语言编写，提供了一种频率计的实现方式，开发环境为Quartus ii 13.0，初学verilog HDL语言的同学可以参考下-FPGA procedures, verilog HDL language, provides a way to achieve a frequency meter, development environment for Quartus ii 13.0, beginner verilog HDL language students
FPGA_Uart
- FPGA程序，verilog HDL语言编写，包含AD转换和串口发送程序，由于AD芯片种类繁多时序迥异，故主要参考串口发送程序。本程序使用quartus ii 13.0 编写。-FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
fpga-nois
- 里面包含fpga的4个noic核 verilog(i2c,rs232,can,8051)。测试过不错-Which contains the four noic nuclear fpga verilog (i2c, rs232, can, 8051). Tested good
fpgahdl_xilinx-edk.tar
- xilinx zynq 7000 FPGA demo-xilinx zynq 7000 FPGA demo