资源列表
number_mod
- 以verilog设计最大为99数字在2个数码管资源上的显示，采取的方法是同步动态扫描。-Verilog design to a maximum of 99 digits displayed on two digital resources, the approach is synchronous dynamic scanning.
20_lcd
- 一种基于verilog和quartusII的液晶显示驱动的封装，LCD（12864）封装。-Verilog and quartusII based LCD display driver package, LCD (12864) package.
bahe
- 采用verilog设计的拔河比赛，在QuartusII9。0仿真验证并在DE2上测试过-Using Verilog to design the tug of war, in QuartusII9. 0 simulation and test on DE2
project
- VHDL编写的ATM代码,能实现全部的功能，经过了测试和仿真。-VHDL code written in ATM, can realize all the functions, after the test and simulation.
syncram
- verilog rtl and testbench code for single port sync ram
alarm
- vhdl alarm design code-vhdl alarm design code
atm_cell
- verilog code for atm_ce-verilog code for atm_cell
cntrlr
- verilog code for bus controller
arb
- verilog round robin arbiter
run
- verilog HDL PARTAN 3E100的流水灯程序-verilog HDL PARTAN 3E100 water light program
segment
- 基于verilog xilinx spartan 的7段管显示-7-segment tube display based on verilog xilinx spartan
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer