资源列表
SRAM
- 利用程序实现SRAM_读写测试，先进行初始化，读写操作，里面的页操作和bank操作。-Using program SRAM_, speaking, reading and writing tests, first initialized, read and write operations, the inside of the page and bank operation.
I2C
- 利用程序实现IIC总线读写数码管显示，实现IIC通信。已调试。-Using digital tube display program to realize the IIC bus, speaking, reading and writing, and realize the IIC communication. Have been debugging.
REG_show
- 利用程序实现红外线解码显示数据码和反码，并调用数码管显示，实现动态变化，动态显示，已调试。-The use of infrared decoding program code and inverted display data and call digital display, dynamic changes, the dynamic display, debugging.
VHDL-language-100-cases
- 关于VHDL语言编程的100个经典例子以及它的详细解释-And its detailed explanation of the VHDL language programming 100 classic example
VHDL-language-tutorial
- VHDL语言的语言基础、基本结构，以及常用电路VHDL程序-Language-based VHDL language, the basic structure and common circuit VHDL program
GPS-signal-C_A-code-and-simulation
- GPS信号C_A码生成算法设计及仿真实现-GPS signal C_A code generation algorithm design and simulation
vhdl-Tutorial
- FPGA入门教程 1数字电路设计入门 2FPGA简介 3FPGA开发流程 4RTL设计 5quartus ii设计-Tutorial 1 FPGA digital circuit design entry 2FPGA About 3FPGA development process 4RTL design 5quartus ii design
vhdl--based-ontesebench
- modelsim环境基于vhdl语言tesebench书写-vhdl modelsim environment based on written language tesebench
ALU
- How to implement a simple 4-bit ALU using VHDL. ALU can perform addition, subtraction, multiplication, logic AND, logic OR and logic NOT of two 4-bit numbers.
vga
- 用verilog设计控制程序从 ROM模块读取图片信息，然后写入 VGA接口。控制程序每隔250ms写入不同的信息至VGA接口，在屏幕上会出现小绿人的动画。-Reading the image information from the ROM module verilog design control procedures, and then write the VGA connector. Control program every 250ms write different messages
run_flash_led
- 用verilog建立一个并行操作的流水灯模块。扫描频配置定为100 Hz，而每一个功能模块在特定的时间内，将输出拉高。-The establishment of a parallel operation of light water module verilog. Scanning frequency configured as 100 Hz, and each functional module within the specified time, the output high.
buzzer_sos_2
- 用verilog产生“SOS信号”，就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。一个比较好玩的源码。-Produce " SOS signal" with verilog, is to have control of the output sequence Moss password " point" , " painting" and " interval." A more fun source.