资源列表
TestBench
- TestBench for stop_watch in VHDL
jijiaqi
- 出租车的计价器，描述了实际出租车的工作状态-Taxi meter, described the state of the actual taxi
huffman
- MP3播放器中的基于霍夫曼（huffman）解码的vhdl语言描述-MP3 player based on the Hoffmann (huffman) decoding descr iption language vhdl
bidir
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
module-paomadeng
- 一般是指各种发光二极管，如主板和主机箱上的指示灯。开机后用来指示各种工作状态。-Generally refers to a variety of light-emitting diodes, LEDs on the motherboard and the main chassis. The boot is used to indicate a variety of working conditions.
Adder
- 本代码为用三种方法实现verilog加法器代码，在ISE中基于Spartan6仿真成功。-This code is used three methods to achieve adder verilog code, based on the success in the ISE Spartan6 simulation.
verilog
- this soure is verilog source. this soure is used to check ber.
ADD6
- 此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to ac
faddsub
- FPU adder / subtractor it is confirmed to work at 32MHz by Spartan-6 SP605.
weitebi_notes
- 维特比译码 ，说明比较详细， 用于卷积的译码，很不错-Viterbi decoding, a more detailed descr iption
fifo2
- 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
chuanbin
- 对信号进行串并转换，使其分成I,Q2路输出信号 -String and convert the signal to make it into I, Q2 output signal