资源列表
32位-33M 从模式(target)PCI接口参考设计_lattice
- 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32 / route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
led_flow
- 跑马灯的VERILOG程序编程，实现了数码管的一次点亮-VERILOG programming Marquee achieve a digital one is lit
prueba
- Contador de 0000 a 3456 con carga y reset
vhdl-complement
- vhdl交通灯控制电路实现，和LCNT8实现，程序为单进程，可读性好，技巧性高。-vhdl traffic light control circuit and LCNT8 achieve the program as a single process, readability skill.
ISE
- 主要介绍了FPGA开发工具ISE的使用方法，介绍的很全面。-Introduces the ISE FPGA development tools to use to introduce very comprehensive.
Xilinx_ISE6.1i_study
- XILINX_ISE快速入门简明教程，内容简明易解，是初学者的必备教程。-Quick Start Guide XILINX_ISE concise, simple easy solution content is an essential course for beginners.
pid-controller-report
- The Laplace transform is an integral transform perhaps second only to the Fourier transform in its utility in solving physical problems. The Laplace transform is particularly useful in solving linear ordinary differential equations such as those aris
ECE572_SS
- 扩频通信开源项目接收机的源码，对于工程很有帮助，附带说明文档ppt-Source spread spectrum communication receiver open source projects for engineering helpful, with documentation ppt
COA_PRO
- 简单MIPS流水线指令集的verilog实现。初步实现了branch 的功能。-implement of Pipelined MIPS processor
xapp716_release
- 基于FPGA的SATA控制器，可以完成SATA1.0协议-FPGA-based SATA controller, you can complete SATA1.0 agreement
Image_Filter_An_Image_halftone
- Image_Filter_An_Image_halftone is performed over data loaded into the on board RAM and presented on a VGA monitor-Image_Filter_An_Image_halftone is perf ormed over data loaded into the on board RAM and p resented on a VGA monitor
Counter
- 计时器的设计，在Quartus II上运行通过，简单易用，主要是For NJU CSers-The design of the timer, run by the Quartus II, easy to use, mainly For NJU CSers