资源列表
4_31
- 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
状态机例子
- 状态机的典型应用实例
2ddct
- 这是一款比较好的关于可编程逻辑器件的状态机源代码-This is a good comparison about programmable logic device of the state machine source code
xyj
- 洗衣机系统，二极管十进制显示倒数时间，流程，注水，洗衣，排水-Washing system, the diode decimal display the countdown time, process, water, laundry, drainage, etc.
4-bit-adders
- four bit adders vhdl code
8bitRISCCPU
- 该文件是8位CPU设计硬件描述语言，对于初学者来说可以作为参考-The file is 8-bit CPU design hardware descr iption language can be used as reference for beginners
CaculatorBasedonVHDL
- 用VHDL编写的计算器，供下载到学习板上使用，芯片型号请在工程中查看。可以实现加减与或比较-Written by VHDL calculator, available for download to learn to use the board, the chip model in the project view. Comparison of addition and subtraction can be achieved with or
pspice
- 学习，通过学习噪声等让整个系统工作的更为稳定-for learn
digital_comparator1
- vhdl code for comparator
qnr_verilog
- 量化取整QNR内部主要包括一个divider模块及产生数据输出有效和循环结果到最近整数的电路，包含仿真结果图。-Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in
ata.tar
- 硬盘接口的硬件实现，VHDL和Verilog是吸纳的，带有文档！
muart
- mini_uart- transmitter, receiver and a baud.