资源列表
xu
- 序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器
chipscope_pro_siotk_10_1_ug213
- XILINX赛灵斯chipscope_pro_siotk_10_1_ug213使用手册，讲得挺详细的。-the introduction of XILINX chipscope
dongmiaobiao55
- 基于FPGA的verilog语言描述和数码管显示时钟，并可以通过按键调节时间。-Clock verilog language to describe and FPGA-based digital tube display and buttons to adjust the time.
DDS.rar
- DDS信号发生器，利用VHDL实现，可根据频率控制字的改变输出不同频率的信号，最高可到达10MBPS,DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
4646413214
- 用32位NiosII处理器实现RS232通信，可以给初学者一个借鉴。-NiosII with 32-bit processors to achieve RS232 communication, can give a reference for beginners.
elevator
- 六层电梯控制，与实际电梯的运行逻辑一致，开门后5s自动关门（注：无快速关门和开门功能）-Six-story elevator control, consistent with the actual logic of operation of the elevator opened the door automatically closed (Note: No quick closing and opening function 5s)
mimasuo
- FPGA电子密码锁，基于VHDL编程语言，可实现报警等功能，方便实用。-FPGA electronic locks, VHDL-based programming language, can be realized the alarm function, convenient and practical.
user-guide
- xilinx用户指南for ML505/ML506/ML507-User Guide
lab3_files
- 基于FPGA 计数器的分析及源代码 和怎样写testbench-FPGA counter-based analysis and source code, and how to write testbench
pinlvji
- AT89c51 1602 可以分频的频率计，最大可以测量98MHZ,程序部分设计得精良！-AT89 c 511602 the frequency that can divide repeatedly account, biggest can measure a 98 Mhz, the procedure part designs excellent!
开源软核处理器OpenRisc的SOPC设计
- 开源软核处理器OpenRisc的SOPC设计,开源软核处理器OpenRisc的SOPC设计
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo