资源列表
clock
- 数字秒表计数 vhdl 译码器 分频器 计数器 报警器-stopwatch counter
clock
- 基于FPGA的电子钟的程序设计，包含定时闹铃年月时的现实。-FPGA-based clock programming, include the reality of time when the alarm years.
sjcj
- 通过ADC0809对模拟信号进行采样，然后将转换好的8位数据迅速转存到FPGA内部存储器中，同时增加一个锯齿波发生电路，扫描时钟与地址发生时钟一致。由此完成一个示波器功能！-Through ADC0809 carried out on the analog signal sampling, and then a good 8-bit data conversion转存到rapid internal FPGA memory, at the same time increase the occurr
threelift
- 利用VHDL语言实现三层电梯的程序，模拟现实生活中电梯的工作原理-Three elevator use VHDL language program, simulate real life works elevator
实验8 含异步清零和同步使能的计数器的设计
- 该压缩包内是一个含异步清零和同步清零的计数器，内还有源代码以及说明文档
8086的基础实验代码
- 8086的基础实验代码，内容为8255的应用和存储器的应用。包含和电路图，实验代码，实验要求文件-8086 on the basis of experimental code, content and applications for the 8255 application memory. Include and schematics, experimental code, test requirements document
clock_domain_process
- 一种将异步时钟域转换成同步时钟域的方法，可节省资源，避免格雷码转换。-A will be converted to asynchronous clock domain synchronous clock domain methods, can save resources, and avoid the Gray code conversion.
Modelsim
- Modelsim的使用方法，适合新手学习，有详细的操作方法和例程-Modelsim to use, suitable for beginners to learn, detailed operating methods and routines
uart_fifo_transceiver_verilog
- verilog UART FIFO 自发自收 自己验证过 基于EP1C3T开发板的-Verilog UART FIFO internal loopback； tested； based on EP1C3T
vga
- Link the VGA adapter located in the altera DE2board to a monitor
addram
- 小型加法器，并实现结果存储，通过多个存储元件，对32位二进制数进行存储-Small adder, and stores the results achieved through multiple storage devices, the 32-bit binary number for storage
uart
- 基于FPGA的UART程序设计，VERILOG HDL语言编写，可实现串口通信，波特率为115200。已通过串口调试助手验证。-FPGA-based UART program design, VERILOG HDL language, enabling serial communication baud rate to 115200. Has been verified through the serial debugging assistant.