资源列表
Verilog_ex4
- 基于FPGA的按下key1键，led0显示SOS信号实验，选用DE1实验板。-Press the key key1 based on FPGA, led0 experiment shows SOS signal
uCore_120rel_vhdl_f
- uCore architecture (VHDL and Forth sources). MicroCore s top priority is simplicity and understandability. MicroCore is rooted in the Forth language but it is not confined to execute Forth programs – it is a pretty good general purpose processor an
Quartus-II-Design-Series_Timine
- quartus 2的学习资料，主要说的是设计实验中的时序分析-quartus 2 learning materials, mainly the timing analysis in the design of experiments
mmp
- 电子密码锁设计， （1） 设计一个开锁密码至少为4位数字（或更多）的密码锁。(Electronic puzzle lock)
minimips_ml1059_synth
- MiniMIps design - Contains verilog/vhdl code and relevant FPGA files
quartus2qq
- 这里是对PFGA的软件Quartus2的介绍，并以其他方式来分析。更全面的了解这个软件-Here is PFGA software Quartus2 introduction, and in other ways to analyze. More comprehensive understanding of the software
RS232_LCD_display
- 基于FPGA的RS232串口控制LCD数据显示源程序-RS232 control of LCD display.
signal_detector
- A behavioral descr iption of a noise cancellation based on audio detection or RF detection, written in a synthesizable subset of VHDL.
Experiment01
- VERLIOG 基本 LED 测试程序 适合新手-VERLIOG LED test program for novice
i2c_vhdl
- i2c协议 vhdl语言 适合对i2c接口外设通信-suit for i2c port communication
basys3_timing
- 基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL-Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL
D_AGC2
- FPGA数字AGC(帮同学做的毕业设计)