资源列表
Chapter-5
- FPGA Prototyping by VHDL Examples Chapter 5
opencore_crt
- 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
dds-example
- Test ADC 1407 and DAC 2604
FPGA_DDS
- FPGA中实现信号发生器,即DDS,代码简洁,精练,非常适合学习,已经经过验证.-The FPGA signal generator, or DDS, the code simple, concise, very suitable for learning, has been verified.
LCD-controller---Nghia
- different code for lcd controller using de2 board with vhdl lanuage
Baseband_line_code
- 基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码-Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code
chengfachufa
- ISE13.2的SPARTAN-3E 乘法除法器-ISE13.2 the SPARTAN-3E multiplication Divider
fir_16
- 基于FPGA FIR滤波器的设计研究，是一个16阶的数字滤波器-FPGA FIR filter design based on research。FPGA FIR filter design based on research, FPGA FIR filter design based on research。
DDS
- 基于FPGA的DDS详细设计方案（附带详细设计方案及代码）-DDS-based FPGA detailed design (with the detailed design and code)
Exp6-VGA
- 通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show
1
- verilog编写的11阶FIR数字滤波器-The 11 order FIR digital filter Verilog prepared!!!!!!!!!!!!!!!!!!!!!
the-use-of-Quartus-and-IP-core
- QuartusIP核的使用,很适合初学者使用-the use of Quartus and IP core