资源列表
spi_master_slave
- 同步串行数据传输SPI的源代码，它可配置成主机或者从机，挂在总线上。-Synchronous serial data transmission the SPI--s source code, it can be configured as host or slave, hanging on a bus.
dma_ahb_latest.tar
- AHB DMA verilog源码 AHB总线 DMA接口源码(AHB bus DMA interface source code)
LAB5new
- This a lab of processor-This is a lab of processor
sanfenpin
- 这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside
vga-example
- Basic VGA implementation on the Altera DE1
abel-hdl
- lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
ofdm_modulation
- Verilog code ofdm modulation
CRC
- FPGA中并行实现CRC-CCITT标准的循环冗余校验码的生成-FPGA to achieve CRC-CCITT standard parallel cyclic redundancy check code generation
TR0114VHDLLanguageReference
- TR0114 VHDL Language Reference
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
VHDL
- Program VHDL is scan keypad matrix 3*3 display to LCD
adjust_clock
- 可调时钟，4个按键调整小时，分，秒，verilog语言。包括测试程序-Adjustable clock, verilog language