资源列表
ISE10.1
- xilinx ISE10.1开发环境指南，叫你如何操作ISE10.1-xilinx ISE10.1
uartfifo
- 串口收发程序，VHDL版本，适用于ALTERA的CPLD -Serial transceiver procedures, VHDL version
VGA-LCD
- 采用VHDL编写的VGA LCD显示。经过了调试仿真，在FPGA芯片上下载成功，并得到了预期效果-Written by VHDL VGA LCD display. After a debugging emulator, FPGA chip in the download is successful, and get the desired effect
EZ-USB-FX2-GPIF-Primer
- EZ-USB FX2 GPIF Primer
USB-COM-routines
- 使用CPLD实现的USB通讯与UART通讯相互转换，USB通讯速率可以达到20M 使用专用USB接口芯片cy7c68013芯片-Using CPLD implementation of USB communication and conversion between UART communication, USB communication speed can reach 20M using the dedicated USB interface chip chip cy7c68013
sdram_verilog
- verilog实现外部sdram读写功能，实测可用(SDRAM read and write function by verilog)
8位二进制转bcd码
- 八进制转换码 硬件描述语言，通过测试，能用(b to bcd code very easy and readily to understand)
8frequency
- 8位数字频率计，利用数字信号发生器产生一定频率正弦波，得到验证。-8 digital frequency meter, proven.
odd_div_ok_
- Learning FPGA students can see, this code USES the VHDL language written by an odd number of frequency divider, not only can learn QUARTUS software, also can better enhance the digital circuit design.
ARM7VerilogCODE
- ARM7 Verilog代码及设计文档，文档说明比较详细-ARM7 Verilog u4EE3 u7801 u53CA u8BBE u8BA1 u6587 u6863 uFF0C u6587 u6863 u8BF4 u660E u6BD4 u8F83 u8BE6 u7E
Mux4
- Mux is designed by verilog use ISE of xilinx.have 4 input
lcd12864testOK
- 用verilog hdl实现的12864液晶显示-12864 LCD verilog hdl