资源列表
DVRcn
- 这是我亲自完成的dvr一体机之后所写的CCTV_10.2寸完整的规格书，已经开始大量了。-This is my personal one machine after the completion of the dvr written CCTV_10.2 inch complete specification, has started a lot of.
QuartusIIanzhuangshiyong
- 软件使用，讲述qurtes具体操作和使用上，编译，写程序-Software, about the specific operation and use of qurtes, compiling, writing programs
wb_conmax_latest.tar
- WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
3
- eda技术与vhdl9第二版）的教程，是我们老师自己做的课件，这是第三章。-eda technology and vhdl9 second edition) of the tutorial, our teachers are to do their own courseware, which is the third chapter.
vhcg_latest.tar
- Viterbi algorithm is the most likelihood decode algorithm of convolution code. Viterbi decoder means the VLSI implementation of Viterbi algorithm. In the area of communication, convolution code is very popular, so how to improve the performance a
RS485verilog
- 这是用Verilog写的RS485通信程序，可以使用，希望大家能够互相交流，-This is a Verilog writing RS485 communication program, can be used, I hope we can communicate with each other,
PGen
- double pulse generator start with trick signal control time between pulse by serial loading
Fast Vector Multiplication
- Fast Vector Multiplication in VHDL with carry save adders and final ripple carry adder
fsl
- freescale 08系列单片机开发及c语言编程简介-freescale 08 Series single-chip development and c language programming brief introduction
Clock
- 多功能时钟，以调试通过，可以直接用，非常适用于FPGA初学者。-Multi-clock, in order to debug through, and can be very useful for beginners in FPGA.
8051vhdl_ip_core
- 8051完整ip内核Vhdl源代码程序。-8051 ip core Vhdl complete source code program