资源列表
da900
- FPGA控制DA芯片产生周期信号,用于简单测试芯片性能-DA chip FPGA control signal generation period, for the simple test chip performance
chuot
- code VHDL/ Verilog for Mouser using FPGA: Xilinx, Altera
IICComponent
- IIC的vhdl实现，用ISE12.1建的项目，读取eeprom的接口代码-using FPGA to communicate with the EEPROM through IIC connector
TIMER
- 用Verilog语言模拟的数字时钟的功能，时分秒工能都有，适合做毕设，完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete
ADC_2_SEQ
- 采集模拟输入，电压动态显示在数码管，已经验证过确实可用，大家可以放心下载-Sampling the analog input voltage dynamic display in the digital tube
jtdxt
- 交通灯系统，有左转灯，译码电路等等，并且已经仿真成功，放心使用。-Traffic light system, there are left turn light, decoding circuit, etc., and have been successful simulation, ease of use.
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
RISC_CPU
- 关于risc cpu 的pdf 希望对学习Risc cpu的人有用-Hope that the study of Risc cpu risc cpu pdf
key_board
- 本设计是实现一个4*4矩阵按键键盘设计，将矩阵按键的按键值通过串口发送到上位机-The design is to achieve a 4*4 matrix keyboard design, the matrix keys to the value of the button to send to the host computer through the serial port
Music_altera
- 采用Verilog HDL设计，在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率，演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
VHDL
- 源代码不同软件对VHDL语法的支持范围是不一样的,以下程序中的某些语句可能不能运行在所有的软件平台之上,因此程序可能要作一些修改,同时务必注意阅读程序中的注释。
plj_book
- EDA，verilog 语言写的频率计，一个是测频，一个是产生一定的频率作为信号源，可在cycloneII 上验证，-EDA, verilog language written in frequency counter, one frequency measurement, one is a certain frequency as the signal source can be verified on the cycloneII, thank you! !