资源列表
ddfsdemo
- 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development enviro
CPUlm3s1627
- lm3s1627 cpu 控制lcd液晶显示 调节数字电位计的抽头数目-lm3s1627 cpu control lcd LCD to adjust the number of taps of the digital potentiometer
tlc5620
- TLC5620C是带有高阻抗缓冲输入的4通道8位电源输出数模转换器集合 用fpga的verilog描述-TLC5620C with high input impedance buffer 4-channel 8 collection of power output digital-to-analog converter using fpga verilog descr iption
20110507
- LED 16X16閃示燈設計for FPGA-LED 16X16for FPGA control
magicmatrix
- 输出的N*N的表格中每行每列以及对角线都相等-MAGIC MATRIX NULL，it s a magic.
HDL_lecture_notes_verilog_gatech
- Verilog 语言 GaTech大学讲义 ，介绍了verilog基本语法以及基础案例，包含源程序，适合本科硬件描述语言学习参考-Gatech univ lectures of Verilog Language , introduced the verilog basic grammar and basic case, including source code, hardware descr iption language for undergraduate study reference
tutorial-spartan-3e
- tutorial spartan 3e and explain about use hardware in VHDL pragramming.
FPGALED1616
- FPGA驱动1616点阵 运用VHDL语言进行编译得出相应图形，文字-Lattice FPGA using VHDL, 1616 driver compile draw the corresponding graphics, text,
shuzishizhong
- 可实现数字时钟功能 用于EDA课程实验 有计时，闹钟，还可自行设置调整时间功能-Digital clock function can be used with EDA time course experiment, alarm clock, can set their own time adjustment function
data_system_design_based_on_FPGA
- 用FPGA設計数字系统，2007年上海FPGA研修班王巍老师讲义-Digital System Design using FPGA, FPGA Shanghai in 2007 Wang Wei, a teacher seminar handouts
DVI_Demo_C3H_PortB
- DVI_Demo_C3H_portB HSMC-DVI card
doc17414x90
- ddr设计控制器，源代码！Verilog代码！-设计控制器，源代码！Verilog代码！