资源列表
Digitalclock_vhdl
- VHDL语言编写的数字时钟代码，环境quartus-Digital clock written in VHDL code, the environment quartusII
vivado_LED_Flow
- 本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。-This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.
Synchronous-Serialization
- 介绍了如何实现Spartan系列FPGA的同步，参考价值很大-Describes how to implement the synchronization Spartan Series FPGA, the reference value of the lot
LED
- 本程序用于XILINX SPARTEN-3E开发板上的LED灯的控制,可以实现控制灯的有规则的闪烁.
dianziqin
- 运用quartus 软件模拟的电子琴，实现按键出现不同音调的音乐。-Quartus software simulation using keyboard, keys appear to achieve different tones of music.
LCD1602shizhong
- 基于FPGA设计的1602显示的时钟，分为几个模块，VHDL语言-FPGA-based design 1602 show the clock, is divided into several modules, VHDL language
elevltor
- 八层电梯的控制器，verilog实现。内附有详细源码。--The controller of three 8-level elevators, designed with Verilog. The design is detailedly represented in the DOC as well as the source code.
CMOS_Transistor_Layout_KungFu2
- Important Layout notes on CMOS Transistor-Important Layout notes on CMOS Transistor,,
USB3.0specification(chinese)
- USB3.0的中文技术规范，包含结构规范和电气规范，适合英文不佳的工程师参考设计。-Chinese USB3.0 specification, including structural and electrical specifications for reference design engineers with poor English.
shuzilvbo
- 数字波形存储器VHDL源码，基于Quartus II开发。
Lab9-Forwarding-Unit
- CSCE2214课程设计，试验9源代码。实现流水线结构的MIPS CPU 16位。配有强大的Forwarding Unit.-CSCE2214 curriculum design, test 9 source code. Implement pipelined MIPS CPU 16 place. With a strong Forwarding Unit.
VGA-LCD
- VGA LCD显示有源代码工程项目文件。-VGA LCD display file source code project.