资源列表
rom
- 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证
3
- SOS响铃verilog程序代码， SOS响铃verilog程序代码-SOS rings verilog program
15_tlc5620dac
- 这是芯片tlc5420数字模拟信号传换实验，实验是用verilog语言写的，希望对大家有用-This is the pass the chip tlc5420 digital-to-analog signal change experiment, experiment verilog language written in the hope that useful. . .
ex5nieuw
- A school big exercise to control traffic lights
banjiaqisheji
- 半加器设计。有用的实验操作报告。EDA有详细的操作步骤-Half adder design. Useful experimental operation report. Detailed steps in EDA
bicycle
- 健身自行车项目的源码和顶层文件。基于quartus5.0，通过验收，请放心使用。-Exercise bike and top-level project source files. Based on quartus5.0, through inspection, please rest assured that use.
Verilog_LRM
- Verilog Language Manual
final_8
- 8. 對於按鍵輸入密碼鎖，假設reset後，七節燈管顯示「0」，而且使用sw1、sw2、 sw3三個，只要按下任何的sw1、sw2、 sw3，都會讓七節燈管顯示值加「1」。-8. For the key to enter a password lock, assuming that reset after the seven lamp displays " 0" , and the use of sw1, sw2, sw3 3, just press any sw1, sw2,
usb-blaster-driver-for-win-7
- USB BLASTER WIN 7 驱动, 绝对能用,亲测-USB BLASTER WIN 7 drive absolutely can pro-test
xapp860
- 16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
project-1
- this a project design and its report of DESIGN AND IMPLEMENTATION OF LOGIC FUNCTIONS FOR DSP APPLICATIONS USING VHDL.