资源列表
FPGA_diaodianbaocunchegnxu
- FPGA掉电保存程序，用于fpga掉电后如何让程序保存-FPGA power-down save the program for fpga power-down procedures for how to save after
asyncwrite
- FPGA异步时序转同步时序模块 位宽（bit） -FPGA asynchronous transfer timing synchronization timing module Width (bit)
zy4668_ybcxjk
- 本源码实现的功能是用VHDL编写异步串行接口设计-The source VHDL implementation of the function is the preparation of Asynchronous Serial Interface
zy4668_music
- 本源码实现了用VHDL语言设计音乐播放器-This source code implements the design using VHDL language music player
ADPCMCodec
- The DVI Adaptive Differential Pulse Code Modulation (ADPCM) algorithm was first described in an IMA recommendation on audio formats and conversion practices [1]. ADPCM is a transformation that encodes 16-bit audio as 4 bits (a 4:1 compression ratio).
ManchesterEncoding
- FPGA实现的曼切斯特编码 VHDL语言-Manchester Encoding based on FPGA
pci_interface
- PCI接口模块程序 veirlog语言编写 有一定的参考价值-pci interface verilog
Verilog_design_135_classic_example
- Verilog的135个经典设计实例,对于FPGA初学者非常有用-Verilog design 135 classic example
Spread-Spectrum-Receiver-code
- 基于FPGA的扩频接收机（直扩）vhdl编写的，最好在quartus环境运行。-FPGA-based spread spectrum receiver (DS) vhdl prepared, the best environment to run in quartus.
caiyang
- 基于VHDL的等精度测频方法，等精度测频方法是在直接测频的基础上，其闸门时间不是固定的值，而是被测信号周期的整数倍，即与被测信号同步的测频方法。-VHDL-based method of equal precision frequency measurement, and other precision frequency measurement method is based on the direct frequency measurement, the gate time is not a
tiaozhijietiaoqi
- 调制解调器（全数字）vhdl程序，包含工程文件可直接编译-Modem (digital) vhdl program, including project files can be directly compiled
firlvboqi
- fir滤波器设计，是MATLAB设计的vhdl转换-VHDL fir digital filter design, MATLAB-based design of the conversion