资源列表
dengjingdu
- 等精度测量，频率越高精度越高，每一秒取一次数，然后经过乘除法实现，FPGA功能前更大的。还用到STM32 SPI通信(The accuracy of measurement, the higher the frequency accuracy is high, every second to take a number, then after multiplication and division, FPGA function more. STM32 SPI communications are
ifir_64
- verilog hdl, quartus.64阶的简单回声抵消器，采用的是基本的LMS算法，简单改进，可用于初期了解。功能背景是对通信领域中，比如打电话时自己的声音到达对方经对方环境多径反射又传回自己这边，即回声。为将回声消除采用回声抵消装置。-64 steps a simple echo canceller is used in the basic LMS algorithm, a simple improvement, can be used for the initial understa
IntegratedElectronics_MillmanHalkias
- THIS BOOK IS SPECIAL FOR ONE WHO WANTS TO SEE THE DETAILS OF ELECTRONIC COMPONENTS LIKE RESITORS
led4
- 数码管动态显示，显示的字符大概14位，动态扫描时间1ms，还是挺好用的(Digital tube dynamic display)
DA_fir_parrel
- 用FPGA实现并行分布式算法的VHDL程序，采用优化结构实现，功能正确-FPGA implementation using VHDL program parallel and distributed algorithms, realized by optimizing the structure and function correctly
information_box_code1.10
- jibengongnengverilog(jibengongneng verilog)
VHDL
- 这是一个关于VHDL的初步完整教程，对初学者很有帮助。-This is the initial complete tutorial on VHDL, useful for beginners.
DDS
- 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来(Verilog realizes DDS Signal Generator)
pc8_1
- MAX+PLUS II BASELINE Version 8.1 Software
mt9d112_ddr2
- 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
project_fir_test
- 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
SOPC-book
- 一本关于设计SOPC的书，讲的很详细，看后很有收获。-SOPC a book on the design, speaking in great detail, looking after the great harvest.