资源列表
chengxu(vhdl)
- 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Prueba_RS232
- Its only a schematic of probe to complete the sending of data through rs232
Verilog
- Verilog数字系统设计教程夏宇闻例题源文件-Verilog Digital System Design Education Chengxia Yu Wen example source file
LCD-display
- fpga的键盘阵列LCD显示程序，包括vhdl文件，顶层文件和工程文件-fpga array of keyboard LCD display procedures, including vhdl files, top-level files and project files
sockit_owm_latest.tar
- 1-wire master written in Verilog HDL, ready for integration into a FPGA or ASIC based SoC. A port of the 1-wire Public Domain Kit (version 3.10r2) from Maxim is also provided, with all the code required for integration into the Altera development
binary-and-gray
- 二进制码和格雷码互相转换verilog源码-Binary code and Gray code conversion verilog source
DDRSDRAM_MT46V32M16TG
- ddr控制器 对DDR实现读写控制-ddr control
Digital----design
- vhdl三层电梯设计及Quartus_II仿真实验-Digital electric technology course design- elevator automatic control system
EDA
- VDLH课后答案及详细分析，给予学生满意的答案-VDLH after-school answers and detailed analysis, to give the students a satisfactory answer
8sc
- 8位所存显示延时源代码，较完美诠释锁存艺术-8-bit display delay kept the source code, the more perfect interpretation of the latch Art
ledall
- 实现了LED点阵上的汉字的动态显示设计,通过修改rom模块能够改变所显示的汉字-To achieve the dynamic LED dot matrix Chinese characters display design, by modifying the ROM module to change the display of Chinese characters
lift
- 电梯控制程序，按钮控制电梯的上下，拨玛开关设置楼层。-Elevator control procedures of the upper and lower elevator button control, set the dial switch floors Ma.