资源列表
61IC_S2682
- verilog编写 以E2V的CCD 芯片的核心图像采集系统-verilog prepared by E2V CCD chip' s core image acquisition system
Verilog
- verilog数字系统学习教程，设和不同人群，通俗易懂，共同学习进步-verilog digital system tutorials, design, and different groups of people, easy to understand, common learning progress
Verilog数字系统设计教程(第二版)夏宇闻
- Verilog学习基础书籍，推荐其第四部分作为手册查阅(Verilog based learning books, recommended the fourth part as handbooks)
Verilog数字系统设计教程(第二版) 夏宇闻
- 一本很好的Verilog语言学习工具书，详细介绍了Verilog语言，状态机等基础知识(A good tool book for Verilog language learning)
UART_proj
- 串口发送接受功能，上位机发送消息给FPGA，FPGA接收后将相同的消息发送至上位机。-A serial port to send in function, PC sends a message to the FPGA, FPGA after receiving the same message is sent first place machine.
RC.tar
- Remote Controlled Car
SV-Priority
- system Verilog priority
brickbreak
- 自行修改后的打砖块游戏，采用Altera DE2开发板，PS2键盘输入，VGA显示输出，回车键复位，空格键开始，小键盘46键控制左右方向-Self-modified Arkanoid game, using Altera DE2 development board, PS2 keyboard input, VGA display output, reset the Enter key, space key to start, keypad 46 keys to control the left
DE2_WEB
- 用DE2板子实现的音频分析器,需要安装quartus2,硬件需要DE2的板子
DAC
- DACADC资料，10bit300MSsDAC6V输出摆动； 10bit500MSPS分段DAC性能优化；用DAC产生Nyquist-WDM信号等-DACADC information, 10bit300MSsDAC6V output swing 10bit500MSPS segmented DAC performance optimization produced by DAC Nyquist-WDM signals
VerilogHDL_module
- VerilogHDL那些事儿_建模篇和Verilog_HDL_那些事儿_时序篇v2是一个系列-VerilogHDL those things _ modeling and Verilog_HDL_ of those things _ timing is a series of V2
wu
- 通信原理基于VHDL的课程设计，基于CPLD_FPGA的数字通信系统建模与设计（通信课设参考书）-VHDL-based communication principle of curriculum design, digital communication system based on CPLD_FPGA Modeling and Design (Communications course design reference)