资源列表
divider
- 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
VHDL1
- 数字电子时钟中，秒和分要求要有60进制计数器和24进制计数器，此为60进制计数器-Digital electronic clock, the seconds and sub-band requires 60 counters and 24-ary counter, this counter is 60 hexadecimal
KeyDisplayUnit
- vhdl实现按键功能，包括消除按键抖动、长时间按键、按键识别等功能。-vhdl achieve key functions, including the elimination of key jitter, long key, key identification features.
input
- input file vhdl downloac gfghfkhhgckhjhhjghbnvgfcvgbnh
rs232
- 用quartus仿真rs232的接收发射波形-quartus rs232
VHDL-to-design-detector
- 用VHDL语言设计一个序列“111010”的检测器和该序列的发生器-VHDL language " 111010" to design a sequence detector and the sequence generator
chuan_to_bing
- 16位A/D转换程序，使用MAX+PLUS2做的，用状态机做的，但不够完善，望大家见谅
crc8
- 8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 -verilog of 8bit error checkout
vendingmachine
- vendingmachine vhdl code
multiplier54
- this code is for 4*4 array multiplier in vhdl it is vhd file that works very we-this code is for 4*4 array multiplier in vhdl it is vhd file that works very well
fifo
- 一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，产生FIFO为空、满、半满、溢出标志。-A synchronous FIFO, the FIFO depth of 16, each storage unit width of 8, asked to produce the FIFO is empty, full, half full, the overflow flag.
vga256
- 本代码是用于Xilinx FPGA 开发板 开发实验的 vga256 verilog源代码 -This code is used for Xilinx FPGA development board developed experimental vga256 verilog source code