资源列表
spi_master
- 基于CPLD/FPGA的SPI控制的IP核的实现spi_master
btn_led_1
- cyclone2-xp开发板的蜂鸣器变频变频音乐,流戏流水灯程序源码,流歌（liuger）开发板光盘上的-cyclone2-xp development board buzzer variable frequency inverter music, streaming play of light water program source code, flow (liuger,) on the development board CD
IIR
- 使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过-Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter descr iption has been run through
caiyang
- 数字视频光端机发送端采样过程编码二十字有木有-Digital Video Optical sending end sampling procedure coding
decrypt_8
- This file is top level entity of decrypt_8 project. This project is 8_bit decryption for TEA algorithm. You can change number of bits (at least 32 bit for TEA). This project is only for one round. You should use input as encryption output so that you
ps2
- ＰＳ／２通讯协议是一种双向同步串行通讯协议。通讯的两端通过Ｃｌｏｃｋ（时钟脚）同步，并通过Ｄａｔａ（数据脚）交换数据。任何一方如果想抑制另外一方通讯时，只需要把Ｃｌｏｃｋ（时钟脚）拉到低电平。一般两设备间传输数据的最大时钟频率是３３ｋＨｚ，大多数ＰＳ／２设备工作在１０～２０ｋＨｚ。推荐值在１５ｋＨｚ左右，也就是说，Ｃｌｏｃｋ（时钟脚）高、低电平的持续时间都为４０μｓ。每一数据帧包含１１～１２个位。
mutiplier_4bits
- 通过移位相加，实现两个数的相乘。通过一个内部寄存器存储得到的积。--- it multiplies a 5_bit multiplicand by a 5_bit multiplier to give -- an 8_bit product -- -- aim: to master the method of mutiplier "shift and add to realize the mutiplier" --
sdram_initializer
- sdram模块控制功能，读取nop的sdram的机器- This module takes care of write, read and NOP state machine of SDRAM controller
Full_Add3
- full adder 3 bit test for vhdl
CORDIC
- CORDIC数字计算机的设计，即坐标旋转数字计算机-CORDIC digital computer design, that coordinate rotation digital computer
PCK_CRC4_D4
- E1成帧模块，使用VHDL语言设计中的CRC4校验码生成模块-E1 framing module, using the VHDL language design CRC4 check code generation module
jiao-tong-deng
- 用vhdl语言编写的交通灯程序，分主干道和支干道-Traffic lights program written in vhdl language , sub- main roads and branch roads。