资源列表
step_motor
- 步进电机定位控制系统VHDL程序,可以进行步进角的倍数设定,激磁方式的选择
VGA_module
- 基于verilog语言编写的VGA协议的程序，用以驱动VGA接口的显示屏-Based verilog language VGA protocol procedures to drive VGA display interface
cache
- 缓存器 cache verilog 欢迎下载偶-cache verilog
1
- 使用force和release语句，这种方法不能准确反映双向端口的信号变化，但这种方法可以反映块内信号的变化。具体如示：-Use of force and release statements, this method does not accurately reflect the bi-directional port of the signal changes, but this method can reflect the changes in the signal block. Spec
uart
- uart - veiloghdl rx, tx, baudrate-uart- veiloghdl rx, tx, baudrate
shuzizhongvhdl
- 原创,基于VHDL的数字钟代码(各功能模块请自己完成)
UART
- C8051F系列单品机，uart端口通讯实验，希望对初学者有帮助-the uart of C8051F
8255_1
- It is about the VHDL code of 8255 and it has got the code of it. SO please enjoy
ISEuart
- 实现串口通信，Verilog语言，ISE开发环境，实现8字节的传输-Uart transition
cache
- 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
uart-txblock
- vhdl实现了UART的数据发送，将八位并行数据转成串行数据输出，并加上起始位和奇偶校验位，停止位。-vhdl UART data transmission realized, the eight parallel data into serial data output, plus the start bit and parity bits, stop bits.
sd_ctrl
- verlog实现的sd卡控制程序，已经在quartus下面编译验证通过-Verlog implementation of the SD card control procedures, has been compiled under the quartus validation