资源列表
TimingController
- 能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver-LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver
lpc_top
- FPGA实现LPC总线读的动能，Verilog语言-FPGA implementation of the kinetic energy of the LPC bus read, Verilog language
mictor20110113
- ddr控制参考代码,串口通信可以基于此进行二次开发,fpga参考设计，对ddr设计开发有一定的帮助-ddr controller ref code
ds18b20_319
- 用verilog实现ds18b20_319温度传感器实验，检测环境温度，通过数码管显示出来-Verilog achieve ds18b20_319 temperature sensor experiments, testing the ambient temperature by digital display
SDRAM
- 这篇文档主要是介绍了SDRAM的相关原理，以及时序的一些描述，是学习SDRAM的一篇不错的文档-This document mainly describes the relevant principles SDRAM, as well as the timing of some descr iption, is to learn a good documentation of SDRAM
half_adder
- 半加器的VHDL实现，包括Testbench的编写，可供新手参考-Half Adder VHDL Testbench
Sinusoidalsignalgenerator
- 正弦信号生成行为级描述，结构级描述全套，适合仿真-Sinusoidal signal generated behavioral descr iption, a full set of structural level descr iption for simulation
Game_HLD3
- 基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
UART
- IM DESINING VHDL COD EIN IS THIS CODE IS GOD AND TESTIN VERY GOOD
VHDLjianpan
- 一个VHDL键盘的设计，有去抖，能稳定在LED上显示。程序都已变好，你可以借鉴一下。-VHDL design of a keyboard, and to tremble, to stability in the LED display. Procedures have been changed for the better, you can learn from you.
TCAM
- FPGA VERILOG TCAM (ternary content addressable memory)是一种三态内容寻址存储器，主要用于快速查找ACL、路由等表项。-FPGA VERILOG TCAM (ternary content addressable memory) is a ternary content addressable memory, mainly used to quickly find ACL, routing entries.
firOK
- fir滤波器的设计，此滤波器 Fs为44kHz,Fc为10.4kHz。