资源列表
fft
- fft的计算原理以及图标说明，包括寄存方法-fft
ddssheji
- 这是用VHDL语言编写的一个DDS频率合成器的源程序-VHDL prepared a DDS DDS source
taxibillingsystemVerilog
- 在Quartus II 5.0环境下，开发此出租车计费系统，可以对出租车的不同情况计费，精确至0.5元-In Quartus II 5.0 environment, the development of the taxi billing system can be of different situations on the taxi billing, accurate to 0.5 yuan
jianpanyima
- 利用FPGA编写的键盘译码程序，可以看看！-Keyboard decoding process can take a look at!
pinjiniushuaxin
- 频率计 课设 可测4000hz 可选档位自己设计 供大家参考-Frequency meter course set measurable 4000hz optional stalls of their own design for your reference
vhdl-cpu-16-bit
- VHDL processsor 32 bit ALU SRF BUS DATA ADRESS C16 System On Chip Architecture
taxi1
- 出租车计价器，简单、方便，采用verilog hdl语言编写，所用平台是MAXPLUS软件-Taximeter, simple, convenient, using Verilog HDL language, by using the platform of software Segments
VHDL-ppt
- VHDL的重要PPT资料,对初学者非常有益处
counter_led1
- 三段式状态机控制LED以不同的频率闪烁，时候入门，经典-Three-state machine controls the LED flashes at a different frequency, time entry, classic
Quartus-II-10.1-Handbook--Volume-3
- design debugging of VHDL-the design of limited status in VHDL
robertvision
- 基于FPGA的嵌入式机器人视觉识别系统模块源代码，也包括了所有硬件设计资料，是VERILOG格式-Embedded FPGA-based Robot Vision Recognition System module source code, including all hardware design information
Verilog_CLOCK-v2013.10.07
- 六位数码管显示的电子钟，可以调整时间，通过验证-Six digital display electronic clock, you can adjust the time by verifying