资源列表
ASIC_Design_Flow_Tutorial_with_synopsys
- Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
ACM
- 用verilog编写了宽带自适应传输，包括加扰，解扰(Broadband adaptive transmission is written in Verilog)
Performance-Analysis-of-(63-56)-Bch-Code-Using-mu
- BCh code for error correction contro-BCh code for error correction controll
edaok_UART_FPGA
- 用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
Ethernet
- xilinx xupv5-110t ethernet mac调试，工程已做好，直接可用。-xilinx xupv5-110t ethernet mac
FIR
- 实现FIR滤波，利用Verilog语言对其进行了设计 -FIR filter implementation using Verilog language design was carried out
PluseMaker
- 秒脉冲发生器 频率可调 带数码管显示 带约束文件 配合 Xilinx FPGA-Second pulse generator frequency is adjustable with digital display
Next186_SoC_Pipistrello_ISE14.7_09Feb2017
- Next186 x86 for Pipistrello
MAX263-MAX268
- D板的数字可编程有源滤波模块设计，MAX26 系列数字编码式滤波器的使用方法-MAX263，MAX264，MAX265，MAX266，MAX267，MAX268
JXJ_TOP
- 用VHDL语言建立的简单计算机工程，经测试可以正确。-VHDL language to establish a simple computer engineering, has been tested correctly.
A4_Mod_Top
- 多终端点歌系统实验，我们可以使用串口外设发送0~9这10个数字控制蜂鸣器发出不同的音调，可以使用PS/2外设发送0~9这10个数字控制蜂鸣器发出不同的音调，还可以使用红外外设发送0~9这10个数字控制蜂鸣器发出不同的音调。(Multi terminal point song system experiment, we can use the serial port peripherals to send 0~9 10 numbers to control the buzzer to send d
DE2_SD_Card_Audio
- 本程序由verilog语言写成，主要实现的功能是对于sdcard中的音频文件的读取及播放-This program is written in Verilog language, the main function is to read and play sdcard audio file