资源列表
SDRAM
- 模块采用网上的模块，自己进行测试，在测试过程中了解其使用方法。经过测试，存进去的数据正确读取出来。-The module uses online modules, test yourself, to understand its use in the testing process. Been tested and stored inside the data read correctly.
DDR2_XILINX
- xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中-xilinx FPGA design needs DDR2 files that can be applied to the actual design
FPGA-auto-car-and-arm
- VHDL Verilog编写，实现无线串口通信遥控4自由度机械臂和车身行动驱动。串口命令格式和舵机参数可根据实际需要自行调整-Verilog VHDL prepared to achieve a wireless serial communication remote control 4 degrees of freedom manipulator and body action. Serial command format and actuator parameters can be adju
FPGAVHDLexample
- 是FPGA应用的好列子，本人经过测试的，有USB的I2C的，还有一些经常用的程序，是初学和参考的好帮手
SinGen
- 使用Verilog编写的正弦波生成工程，使用ROM核产生，利用mif文件-Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file
ADC采样oled显示
- 通过12位32单片机ADC采样显示测量电压(Through 12 32 single-chip ADC sampling shows that measure the voltage)
zybo_zynq_audio
- Zybo xc7z010 uation board,ssm6203音频编码器，PC端给音频输入，HPH输出口输出过滤噪音的音频，软件：xilinx vivado, vivado HLS, SDK-Zybo xc7z010 uation board, ssm6203 audio encoder, PC end to the audio input, HPH output port noise filter audio software: xilinx vivado, vivado HLS, SD
BHT800_Programmers_Manual_E1
- denso-bht800数据采集器开发手册，可参考此手册开发程序-denso-bht800 development of manual data acquisition, refer to the manual development process
catapult_useref
- 非常好的catapult学习书, catabult 可用于高级综合，由c产生vhdl/verilog.希望更多同道加入。-very nice book for catabult study
20_lcd
- FPGA实现LCD显示，verilog编程控制-FPGA achieve LCD display, Verilog programming control
uart.main
- 异步串口通信程序，带时序输出，已经验证过了-Asynchronous serial communication program with the timing of the output has already been verified
e3b27184377b
- 效率超高的始终程序，程序简洁易读！希望对你有用-High efficiency of always program, and the program is concise and easy to read! Hope to be useful to you