资源列表
verilog_examples
- verilog的大量例子，含有常用模块，适合初学者学习。-verilog large number of examples, with commonly used modules, suitable for beginners to learn.
WriteDpAddr
- 写DPRAM状态机，Quartus -DPRAM write state machine, Quartus II
ReadDpram
- 读DPRAM状态机，Quartus -DPRAM read state machine, Quartus II
FPGA-rule10
- fpga开发的十大戒律，给FPGA开发的朋友共享一下，让菜鸟少走弯路，给高手一些借鉴-fpga development of the Ten Commandments, to the FPGA development friends to share and let rookie detours, some reference to the master
jiafaqi
- 实现一位全加器的运算，并通过调用模块实现四位全加器的运算-Implement a full adder operation, and by calling the module' s operation four full adder
lattice-FPGAHDMI-
- 实现FPGA与hdmi通信非常有用的开发文档-a perfect doc for develope application between FPGA and HDMI
ledwalk_FPGA_Altera
- Altera FPGA跑马灯程序，入门程序实例-Altera FPGA Marquee program, started instance
cpu-kongzhi
- 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-
RTL
- 256位有符号整数乘法器，个人学习时编写，接口为IPBUS，用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
ISE-12.3-Guide
- 本文为ise12.3详细开发步骤，对新手会非常有帮助的。-This article ise12.3 detailed development steps, the novice will be very helpful.
paobiao_gongyang
- 用verilog语言写的电子跑表，在共阳数码管上显示，八位的，初学EDA，感觉verilog语言好入门，我的QQ：942954258，欢迎与你共赢21世纪-Verilog language used to write electronic stopwatch, were positive in the digital display, eight, and novice EDA, started feeling good verilog language, my QQ: 942954258, w
key_sin
- PS/2键盘加DDS的verilog 设计-PS/2 keyboard plus the verilog design DDS