资源列表
verilog_show10
- 基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者-VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners
V3(2)
- 设计一个7段数码管译码器，带数码管的4位可逆计数器 [具体要求] 1. 7段数码管译码器 使用拨码开关SW3, SW2, SW1, SW0作为输入，SW3为高位，SW0为低位。 将输出的结果在HEX1，HEX0显示。当输入为‘0000’~‘1111’显示为00~15， 2. 带数码管的4位可逆计数器 将实验三的结果在数码管上显示。结合上次实验，将4位可逆计数器，数码管显示，分别作为两个子模块，实现在数码管上显示的4位可逆计数器。-Design of a 7-s
cpu_vh
- 一个大学计算机组成原理CPU的课程设计，比一般的CPU的课程设计多了几种寻址方式，总共六种寻址方式，对CPU的内部问题能有很深的了解。-Principles of Computer CPU of a university curriculum design, the CPU than the average of several courses designed to address multi-mode, a total of six addressing modes, the CPU'
fft
- 一个fft算法的应用,对于初学者对于FFT算法的应用有了很大的帮助-The application of a fft algorithm, FFT algorithm for the application for beginners has been a great help
frequency
- 一个三位或者多位十进制数字式频率计，量程为1KHZ到99MHZ，可以自动换挡-More than three decimal digits or a frequency meter, the measuring range 1KHZ to 99MHZ, you can automatically shift
ledyyw
- 用VHDL实现流水灯，配置管脚，并在FPGA板上得到实现-VHDL implementation of water with the lights, configuration pins, and realized in FPGA board
SRAM--verilogsram
- 在quatus2环境下编写的SRAM读写实验,verilog代码-Environment written in quatus2 SRAM read and write test, verilog code
exp1.5_mux8_1
- 用VHDL及verylog语言设计一个8选一数据选择器，可以在Quartus II中仿真-Language Design with VHDL and verylog a 8-to-one data selector, you can simulate in the Quartus II
ym138
- 这是一个使用VHDL语言编写的138译码器，至于138译码器的功能在此就不赘述了。-This is a 138 using the VHDL language decoder, decoder 138 function as this will not go into details.
adc_top
- AD9480驱动与接口verilog代码-AD9480 driver and interface verilog code
DE2_SD_Card_Audio
- DE2板上读取SD卡，使用nios ii IDE开发环境，可以读取SD卡里面的任何文件系统。-Read SD Card based on the DE2 board,the environment is nios ii IDE
verilog1
- 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed pac