资源列表
alteralvds.rar
- 基于altera系列芯片lvds接口的fpga设计 verilog源码,Series altera-based chip interface lvds source fpga design verilog
eda.rar
- 使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟,The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
uart.rar
- 带自适应波特率发生器UART实现，经过FPGA验证的！,UART baud rate generator with adaptive realization, after FPGA validation!
paobiao.rar
- verilog实现的数字跑表 精确到10ms,verilog digital stopwatch to achieve accurate to 10ms
DDS.rar
- Quartus中实现的DDS 使用的是altera提供的IP core,DDS achieved Quartus using IP core provided by altera
jianbo.rar
- 运用CORDIC算法完成对矢量信号模值及相位信息的运算,The use of CORDIC algorithm for completion of the vector signal value and the phase mode of operation information
uart.rar
- Verilog编写的UART程序源代码。测试成功。支持字符串发送,UART prepared Verilog source code. Successful test. Support string sent
Avalon_PWM_IP_pwm.rar
- Avalon总线下的PWM的IP模块。基于VHDL语言。,Avalon Bus IP of the PWM module. Based on the VHDL language.
m.rar
- 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，,A language with vhdl generator sequence m
hdl.rar
- 双向RAM控制程序,使用VRILOG HDL 编写，简单实用,DAUL RAM control
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
TLC0831.rar
- FPGA对TLC0831的控制程序，实现AD的转换控制和数据的读取。,FPGA control procedures of the TLC0831 to achieve AD conversion control and data read.