资源列表
UART
- FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
AD7938controllor-VHDL
- VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938-VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel
ddsb
- DDS波形发生器，通过改变频率控制字来改变输出波形的频率。波形的数据实现存在ROM表中，通过时钟触发来读取。-DDS waveform generator, by changing the frequency control word to change the frequency of the output waveform. The data waveform ROM table to achieve there, triggered by the clock to read.
8b10b编解码
- 8b10b编解码，aurora协议，遵照xilinx官网文档-8b10b encoder and decoder, aurora protocol
DE2_115_SD_CARD
- DE2-115的SD卡读写实验，基于NIOS和C语言编写的代码-DE2-115 SD card reader test, based on NIOS and C language code
CPLD_DS18B20
- 基于CPLD的DS18B20温度显示程序，可将采集到的温度值通过16位LED或四位数码管实时显示，同时可任意设定温度上下限，实现蜂鸣器告警（该程序已实测成功，内附DS18B20中文资料）-CPLD-based DS18B20 temperature display program can be collected by temperature or four 16-bit digital tube LED display real-time, while lower temperature ca
SignalTap-shiyong
- fpga读写sram（61LV25616），程序附详细注释，包含波形仿真文件及signaltap在线调试文件，并附有文档对程序及signaltap的使用进行了详细说明。 -fpga read and write sram (61LV25616), with detailed program notes, including documents and signaltap waveform simulation debug files online, along with documentatio
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
VGA_Controller
- VGA接口图片显示。可以用在DE2开发板上，可以根据AD芯片修改源代码作移植-VGA interface image display. You can use the DE2 board, you can modify the source code under the AD chips for transplant
LCD12864controller
- 基于 VHDL的LCD12864 控制器设计，Altera 的cyclone II 系列-LCD12864 controller design based on VHDL, Altera cyclone II Series
lcd
- spartan3E开发板LCD开发程序，调试通过-spartan3E development board debugging
USB_Verilog_IP
- USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source