资源列表
OOB_control
- 串行传输协议sata的物理层的控制模块的状态机-Serial transmission agreement of the physical layer control module sata the state machine.
minus
- 一位二进制全减器的设计，分别用原理图输入法和文本输入法，用分层设计的方法完成-A binary full subtractor design, respectively, schematic input and text input method, complete with a hierarchical design method
xsp605_ilinx_mig_ipcore
- 赛林思开发板sp605的内存管理单元的ip核调试通过-SP605 IP core mig
v_verilog
- Verilog VHDL经典实例，完整源码与大家分享。-Verilog VHDL classic example of a complete source to share with you sponser links.
test12864
- 12864的VHDL程序！测试成功的！ -12864 VHDL program! Test successful!
uartverilog
- verilog hdl FPGA vga时序显示经典源程序 很实用的-verilog hdl FPGA vga display timing source code very useful
b_pro3_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
mul64
- Verilog实现的64位乘法器，该乘法器是我所见过的最牛的乘法器、运算快、资源利用少-Verilog implementation of the 64-bit multiplier, the multiplier is the most I have ever seen cattle multiplier, computing faster, less resource utilization
ARM_ALU
- ARM ALU设计，包含相应的VHDL文件及设计所用到的Visio图。-ARM ALU design, the VHDL file that contains the appropriate use and design of the Visio diagram.
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
susliks-project
- 基于逻辑门的打地鼠游戏，其中设置了三关，每关出现八个地鼠-playing susliks with logic gate
vhdl1.rar
- 设计一个四路数据选择器,其功能是将四组不同的数据按要求选择一个输出.输出的那组数据有两个控制信号决定,其真值表如下: 数据选择控制端 输出的数据 Input0 Input1 output 0 0 output0 0 1 output1 1 0 output 2 1 1 output 3, Designs four ways according to the selector, its function is chooses four groups of different data accor