资源列表
K9HCG08DG08.rar
- K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D 三星 4G 8G 16G nand资料,K9HCG08U1D K9PDG08U5D K9LBG08U0D K9MDG08U5D Samsung 4G 8G 16G nand datasheet
Guagle.zip
- QUARTUSII 波形数据(MIF文件)生成器,QUARTUSII waveform data (MIF files) Generator
state_machine_watchdog.rar
- 基于状态机的CPLD/FPGA看门狗程序 难能可贵,State machine based on the CPLD/FPGA valuable watchdog process
ram_16bit.rar
- RAM写入16位，读出16位,并且通过计数器控制ram可以实现读入多个数据,This ram can write 16bits and read 16 bits
OpenSpacewire_090406.rar
- SpaceWire节点逻辑，VHDL，希望有帮助,SpaceWire Node logic, can be used widely
pico04_mem_uart.rar
- picoblaze实现串口通信...难道一定要20个字吗?,implement uart communication base on picoblaze
adc0804_new.rar
- AD0804驱动，使用新的查表方式，可大大的降低数值运算，节省CPLD的资源,AD0804 driver，using a new method_look up table,which can save a lot of resources of CPLD
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
xapp1076
- Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers
DAY07
- verilog 编写的查询法和线反转法举证键盘实例程序-verilog matrix—key
MySDTEST
- 读取F16文件系统的SD卡里面的bmp文件-To read bmp file of F16 file system on SD card
uartfifo
- 串口收发程序，VHDL版本，适用于ALTERA的CPLD -Serial transceiver procedures, VHDL version