资源列表
Ex02_BCD
- 用FPGA实现BCD功能，提供源代码，并配有文字说明。适合初学者看，语言为VHDL语言。-Realizing the ability of BCD with FPGA.Use VHDL.There are also exploin in Chinese,which is suitable to the freshman.
FP_ADDER_SUBTRACTOR
- This is FP_ADDER_SUBTRACTOR.
FP_ADDER
- This a project of FP_ADDER.-This is a project of FP_ADDER.
EDA-digital-clock
- 显示时、分、秒，有手动校时功能，计时过程具有报时功能-Display hours, minutes, seconds, manual timing function, timing processes with chime
aes3_rev1.0
- AES3在altera FPGA上开发的参考案例-AES3 Reference Design v1.0 The AES3/EBU reference design provides both a transmitter and a receiver. The receiver extracts the data and the clock an incoming AES3/EBU stream and stores the parallel audio data and
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench
N_CSMA
- 一种CSMA原理的描述性仿真编程，实现了站点间的类CSMA通信-One kind of CSMA descr iption of the principle of simulation programming class that implements the CSMA communication between stations
AD7612V3
- Verilog Code of AD7612
Bell2
- This an example for control a Bell in VHDL languge-This is an example for control a Bell in VHDL languge
BCDTo7SEG
- This is a example for BCD to 7SEG. This code is wrote in VHDL
Multiplexer
- This a example for Multiplexer. It is wrote in ISE xillin -This is a example for Multiplexer. It is wrote in ISE xillin
Component_instanlations
- This an example for component_instanlations in VHDL languege-This is an example for component_instanlations in VHDL languege