资源列表
AlterMCU8051IP
- 8051IP核 FPGA ALTER公司-8051IP-core FPGA
beipin
- FPGA工程文件，可以实现倍频以及小数倍频功能-FPGA PROJECTION
trigger
- 用vhdl对于GAL22V10编程，实现触发器功能-Using VHDL for GAL22V10 programming, realize trigger function
v
- Verilog写的二分频电路代码，FPGA，实现将输入时钟信号的频率变成原来的1/2-Write Verilog code for the second divider circuit, FPGA, to achieve the frequency of the input clock signal into the original 1/2
crack-81
- 最新QuartusII8.1的补丁，安装它的破解器，可以获得长期使用权-QuartusII8.1 the latest patch, install it to break, and access to long-term use rights
fir_lms
- 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
gsrd_7_1_2
- xilinx下的Gbit级通行参考设计，已经过本人验证-Gbit-class xilinx passage under the reference design, I have been to verify
twice_freqencey
- 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
DMA
- 针对QUARTUS的DMA的VHDL代码实现-DMA Controller Code in VHDL
Device-DNA-Reader
- 基于Xilinx FPGAD SPartan-3an开发板的 DNA Reader参考设计-DNA Reader Base on Xilinx FPGAD SPartan-3an kit
assignmentP2
- 1. Access the relevant reference books or technical data books and give accurate definitions for the following timing parameters: (1) propagation time tPD, (2) transition time tTD, (3) setup time tSU, (4) hold time tHD, and (5) clock-to
my_232
- verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^