资源列表
RX
- 1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
KB-1B-Programs-V3.0
- kb1b开发板配套程序，ASCII码表和液晶图片，程序目录，有Cry1602，蜂鸣器，模数转换，TFT等等。-kb1b development board supporting the program, ASCII code table and the LCD image, the program directory, there Cry1602, buzzer, analog-digital conversion, TFT, and so on.
VHDL_clock
- 关于电子数字钟得FPGA实现，上传来分享一下-Electronic digital clock was on the FPGA, upload to share with you
Crack_QII_11.1_Window11.1
- altera quartus 11.1破解版-altera quartus 11.1破解版工具
FPGA_NES
- 这是用FPGA开发NES游戏机的一些资料， 这份文档目前的版本是 0.01 版，只对 NES 的 CPU、内存、系统概况和 PPU 进行了初步介绍-This is the NES game with the FPGA development some of the information, this document is the 0.01 version of the current version, only t
VGA_Pattern
- FPGA用于控制VGA数模转换芯片ADV7123的Verilog控制代码；实现了VGA的显示时序，输出包括vga_hs,vga_vs,vga_clk,vga_blank,vga_sync,vga_R,vga_G,vga_B-The verilog code for control ADV7123 with FPGA.
flash
- 通过NIOS环境用C语言对Flash进行读写操作，对初学者有很好的参考价值 -NIOS environment by using C language on the Flash read and write operations on the value of a good reference for beginners
DE2_NIOS_Lite_12_flash
- 实现如何在Nios II对Flash进行读写 [SOPC、Nios II、DE2] -Introduce how to read and write the Flash using Nios II[SOPC、Nios II、DE2]
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
8051IP_Verilog
- 8051核，verilog实现。可以直接用在FPGA中，在此基础上可以和用真正的8051一样的进行单片机的学习。-8051 Nuclear, verilog achieve. Can be directly used in the FPGA, in this basis can be used as the real conduct of the 8051 single-chip learning.
eth_send
- 清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
VERILOG-USB2.0IP-core
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files