资源列表
Verilog
- vreilog资料，供大家学习下载，希望大家有什么好的资料共享下，-verilog
Using-PlanAhead-in-project
- 讲述了xilinx公司FPGA高级设计工具PlanAhead 的使用流程。是学习FPGA高级设计的教程。-About the xilinx FPGA design tools the PlanAhead the use process. Is the tutorial to learn the advanced design of the FPGA.
HSMC_breakout_header
- Altera公司的HSMC_breakout 系列的原理图和pcb文件，注意，是capture及pdf格式的原理图和allegro格式的PCB文件，稍微修改修改就可以用在您的设计中，让fpga的硬件设计变得简单和高效。-Altera Corporation HSMC_breakout series schematic and pcb files, note that the capture and pdf format schematic and allegro PCB format file
ir_setup_w7
- 了解TMOD和TCOM原理 知道引脚和定时器、计数器的控制为-TMOD and TCOM to understand the principle that pin and timer control for the counter
A4_Clock_Top
- 24小时制数字时钟，可自行调节时间，能暂停。(24 hours digital clock, can adjust time, can pause.)
verilogpractice1-9code
- verilog练习1-9代码，Sopc中硬件描写语言及程序，以及modelslim软件调试-Exercise 1-9 verilog code, Sopc in hardware descr iption language and procedures, and modelslim software debugging
verilog-ip-core
- verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
OFDM-DESIGN-fpga
- 基于FPGA的OFDM基带系统设计,内容翔实，包含全部源代码-the design of OFDM system based on FPGA
VHDL_study
- vhdl实用教程，经典教程，本书特意做了书签，方便初学者查询-vhdl practical course, classic tutorial, the book deliberately made bookmarks, easy for beginners query
work
- 数字系统设计及VHDL课上用的易于混淆的代码-Digital system design and use of the VHDL code lesson is easy to confuse
OFDM-verilog
- ofdm系统完整源代码，verilog语言编写，在ise平台测试通过-ofdm source code in verilog, run in ise fpga platform
anjian
- 用FPGA实现按键对数码管显示的数字控制，兼有加数、减数功能。使用两个按键及两个数码管。-To achieve key display of the digital tube digital control with FPGA, both the addend, meiotic function. The use of two keys and two digital tube.