资源列表
sqrtcsla
- Carry select adder using square root method.
fifo
- 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
top_ram
- 在quartus环境下调用ram核并对其进行功能时序仿真-ram
ex2_seg7
- 基于FPGA的七段数码管实验，怎样点亮数码管-The seven-segment FPGA-based experiment, how light LED
Evita_Verilog
- Verilog 的非常好用易懂的教学软件。-Verilog very handy and easy to teaching software.
ov5640摄像头模组
- 通过iic总线配置实现5640摄像头图像采集
FPGAOFDM
- 频偏校正算法的ＦＰＧＡ实现源码，相信对大家很有帮助。-Viterbi algorithm for FPGA implementation source code, I believe very helpful to everyone.
multiprocessor_tutorial_final_v1
- 多核处理器系统整个源代码，可以在DE2开发板上运行，请大侠多多指点，-Multi-core processor systems throughout the source code can be run in the DE2 board, heroes lot of guidance, thank you
Example-b8-2
- 学习使用ModelSim对Altera设计进行时序仿真的简单操作步骤。-use vhdl
dianzishejishili
- 电子系统设计实例 设计语言VHDL 实验仪器 杭州康芯gw48eda 开发系统-Examples of electronic system design languages VHDL core experimental apparatus gw48eda Hangzhou Culture Development System
verilog-HDL-learning
- 从零开始学verilog HDL ，包括Altera实验板原理图，xilinx实验板原理图和一些实验源程序-From scratch learn verilog HDL, including Altera experimental board schematic, xilinx test board schematics and source code of some experiments
stopwatch_if
- 用IF语句实现秒表功能的代码，显示范围在000至9-Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.